ECE 275 - Sequential Logic Systems
Fall 2018
Lab 1

Before starting, and before coming to lab, you will need to download Altera Prime, Lite Edition. Select version 18.1, Lite Edition (so we're all using the same version). You'll need to create an account. In addition also download ModelSim and include Cyclone V device support.

The purpose of this lab is to learn more about Verilog and Altera's Quartus Prime software and to use the Altera FPGA development board. In this lab you will design an adder circuit and will display the result using the board's 7-segment LEDs. Your circuit will add two unsigned 4-bit binary numbers which are entered using the board's switches, it will convert the 5-bit binary result (0 to 30 decimal) to two Binary Coded Decimal (BCD) digits, and each of these BCD numbers will be converted to a 7-segment value which is displayed on a 7-segment LED. You will simulate your design, download it to the board, and demonstrate it to the TA. The following will get you a maximum grade of 80. Add 5 points for coming to lab with Quartus already installed on your laptop (see class notes). Add another 5 points by actually performing the simulations (see below). For more credit, add to what is required here (e.g., multi-function ALU, dealing with negative numbers, utilizing LCD unit, etc.).

When you first open Quartus, it may first ask if you want to launch the device installer to add devices, and it may direct you to do so from the Windows start menu. In any case, launch the installer and follow the wizzard (navigating to the Cyclone V device file you previously downloaded), then restart Quartus.

Your design will be in a single project that is divided into multiple modules (parts). These modules all "live" in the same directory (folder), but each module has it's own file name. If you do it the easiest way, each module is pretty simple.

To begin your project go to File -> New Project Wizard. -> Next, then enter project folder and name. Select an empty project. Don't add files yet. On the "Family, Device and Board Settings" select under "Family" the Cyclone V (E/GX/GT/SX/SE/ST). Under "Name filter" type 5CEBA4F23C7, Under available devices you should now have 5CEBA4F23C7, select that and click "Finish".

It will be helpful if you open the "Project Navigator" if it is not already open (View -> Utility Windows -> Project Navigator). Now for each module (described below) create a file by selecting File -> New, then select "Verilog HDL File". This creates a ".v" file, temporarily named Verilog1.v, and opens an editor window in which you can type in your code. (Other types of files in our labs will be: "Block Diagram/Schematic File" (.bdf) and "University Program VWF" (.vwf) files.) You will create ".v" files for the following three modules:

  1. Your first file is the four bit adder. It should add two 4-bit unsigned binary numbers and convert the result to a 5-bit binary number. Section 5.5 (Section 3.5 in 3rd edition Verilog) in the text will be very helpful in writing this code. HINT: Look at ALL the examples in this section, not just the first. BIGGER HINT: If you forgot your text some pages you will need are here (for this and the third module).
  2. Your second file will convert a 5-bit binary value to two (4-bit) BCD digits. See class notes for help on implementing this.
  3. Your third file will convert BCD to 7-segment. This one can be copied verbatim from a figure in the text (Fig. 4.34, pg 219 of 3rd edition Verilog, Fig. 6.38 of other Verilog editions, Fig. 6.47 of VHDL editions). However, you may need to invert the values on the outputs (change 1's to 0's and vice-versa) as our boards use active low outputs (a 0 turns the segment on).

Save each of these three modules then for each, compile and create a default symbol as follows:

  1. Remember to name each Verilog file with the same as its "module" declaration. It will have a ".v" extension.
  2. In the "Files" tab of the "Project Navigator" right click on the file and select "Set as Top-Level Entity".
  3. Compile
  4. Create a symbol for the module: In the "Files" tab of the "Project Navigator" right click on the file and select "Create Symbol Files for the Current File"

Simulate each module:

  1. For the module you want to simulate do "Set as Top-Level Entity".
  2. Compile again
  3. Create new vector waveform file (University Program VWF) and set it up as follows: In the waveform editor, in the blank space under "Name", right click and select "Insert Node or Bus..." -> Node Finder... -> List, then select the inputs and outputs you want included in your simulation (you only need the groups and not the individual lines) and move them to the box on the right.
  4. Set up each input to generate different values (right-click on the input, choose a radix of "Unsigned Decimal," then use the "Count Value" button above and count up by some increment, e.g., 3 or 5)
  5. Under "Simulation" choose "Run Functional Simulation"

After the above three modules are generated, create one more file, this time a "Block Diagram/Schematic File" for the top level of your design to pull it all together. This opens up a drawing area and in this drawing area, right click and do Insert -> Symbol..., and then under "Project" folder you should find the modules you created above. Lay these down in the drawing area. You will need two instances of the BCD to seven segment decoder. You will also need it insert "inputs" and "outputs." You will wire these using "bus" lines which are fatter than skinny lines representing a single wire. A single input or output symbol can represent multiple lines on a bus if you label it appropriately (e.g., X[0..3], or SW[9..6]). To make the pin assignment easier, label the two inputs as SW[9..6] and SW[3..0] and label the seven-segment outputs as HEX5[6..0] and HEX4[6..0]. Create a dummy input and label it as SW[5..4], because (apparently) Quartus seems to mess up the pin assignments if you leave a "gap" in any array.

After creating the above Block Diagram/Schematic File, Compile and Simulate the entire design. Note that you may do a partial simulation (you don't need to try all possible input combinations).

Now you are ready to download your design on to the development board:

  1. Perform Pin Assignments: First download the pin assignment (.qsf) file by right-clicking here and saving this file in your project folder or somewhere you can find it. Select "Assignments" -> "Import Assignments...". Click the three dots after "File name", then navigate to the "qsf" file you just download, select it and press "OK" If you click Assignments->Assignment Editor, you will see that there are many things you can connect to besides the switches (SW[]) and seven segment displays (HEX0[] through HEX5[]). The buttons and leds are the easiest to figure out what they are.
  2. Connect the development board to the host computer by means of a USB cable plugged into the USB-Blaster port.
    Turn on the power to the development board (red button). Ensure that the RUN/PROG switch is in the RUN position (up).
  3. You may see a warning saying the "Device drive software was not successfully installed". In that case go to your Control Panel -> "Hardware and Sound" -> "Device Manager". Double click the entry labeled "USB-Blaster". Right click and then "Update the driver". To find the driver navigate to "C:\intelFPGA_lite\18.1\quartus\drivers"
  4. Select Tools -> Programmer.
  5. Make sure the "Hardware Setup" says "USB-Blaster" (you must have it plugged in)
  6. Click the Start button to program
  7. After the device is programmed demonstrate its proper operation to the lab assistant

 The DE0-CV board, and cyclone V chip data sheets along with more information can be found here. Some online tutorials can be found here

You must demonstrate your working lab to the Teaching Assistant or Instructor, and they will check you off.
To be checked off at end of lab:

  1. Top level BDF file.
  2. Verilog files for adder.
  3. Simulation.