############################
# General Processor Options
############################

nCPUs     = 1           # We have a single core
cpucore[0:0] = 'issueX' # single core

# Parameters
procsPerNode = 1	# our machine is single processor
pageSize     = 4096	# under Linux at least


#################
# Technology
#################
technology  = 'techParam'

[techParam]
tech       = 250                # nm
frequency  = 300e6              # Hz


###############################
#  PROCESSOR CONFIGURATION   #
###############################

# r12k p 13
# int register file
# 3 write ports, 7 read ports
#   each ALU has two read and 1 write
#   addr calc unit has 2 read ports
#   last  read shared between store, jr, and move-to-fp
#   last write shared between load, bal, and move-from-fp
# no rob
# special "condition" file for conditional move instructions

# fp register file
# 3 write ports, 5 read ports
# + adder and mul each has 2 dedicated read and one write
# last read is shared between store and move


[issueX]
issueWrongPath = true	# only if compiled with SESC_MISPATH
inorder        = false  # r12k paper page 1
fetchWidth     = 4      # r12k paper page 1
instQueueSize  = 4      # Renau - This is a different type of structure
                        # !(r10k paper page 33)
issueWidth     = 4  # Renau - By issue SESC means max rename per cycle 
		    # !(from r12k paper, page 1)
retireWidth    = 4  # r10k paper page 33
decodeDelay    = 1  # Renau
renameDelay    = 1  # Renau
maxBranches    = 4  # does this mean max branches we can run through? r12k
bb4Cycle       = 1  # ??
maxIRequests   = 3  # ?? 
interClusterLat= 1  # Renau 
cluster[0]     = 'FXClusterIssueX'
cluster[1]     = 'FPClusterIssueX'
cluster[2]     = 'AddressIssueX' # r12k has separate address queue
stForwardDelay = 1  # ?? 
maxLoads       = 16 # Renau - ld/st share a single queue with 16 entries
maxStores      = 16 # Renau
regFileDelay   = 1  # Renau
robSize        = 48 # ?? r12k doesn't have a ROB but has a 48-entry active list (p9)
intRegs        = 64 # r12k p8
fpRegs         = 64 # r12k p8
bpred          = 'BPredIssueX'
dataSource     = "DataL1 DL1"
instrSource    = "InstL1 IL1"
enableICache   = true 
dtlb           = 'TLB'
itlb           = 'TLB'
OSType         = 'std'

minTLBMissDelay= 50 # ?? Linux reports around 50 instructions for TLB miss
		    # handler


########################
# TLB
########################
# r12k has a 64-entry unified TLB
#  each entry points to two consecutive pages
#  it is fully associative
#  it is not possible to represent this in SESC?
# replacement is done in software.  Often the bottom 8 entries
#  are fixed and the rest is random?

# more info, r12kpaper p16

# also, typically 8 of the entries are pinned to the OS

[TLB]
deviceType='tlb'
size =  64*8		# is this bytes?
assoc = 64		# we want fully-associative
bsize = 8		# block size???
numPorts = 1		# have no idea
replPolicy = 'LRU'	# ??


#
# Pipeline clusters
#

# Int ALU
#
# Either ALU can add/sub/logical/move hilo/trap
#  ALU1 branches, shift, lui, conditional moves
#  ALU2 mul,div
# Load/Store unit


[FXClusterIssueX]
blockName   = "IntWin"
winSize      = 16         #?? 
recycleAt    = 'Execute'  # Recycle entries at : Execute|Retire
			  # it looks like Execute is right for r12k
schedNumPorts = 2  # Renau - 2 execution units max
schedPortOccp = 1  # ??
wakeUpNumPorts= 0  # Renau - No split wakeup/select cycle in R12k
wakeUpPortOccp= 0  # Renau
wakeupDelay   = 0  # Renau
schedDelay    = 0  # Renau 


iALUUnit     = 'ALUIssueX'
iALULat      = 1   # r12k paper, p13

iBJUnit      = 'ALUIssueX'	# Branch jump?
iBJLat       = 1   # r12k paper, p13

iDivUnit     = 'MDIssueX'
iDivLat      = 35	# r12k, 34/35cycles for 32 bit, 66/67 for 64 bit
			# r12k paper, p13

iMultUnit    = 'MDIssueX'
iMultLat     = 6	# r12k, 5/6 for 32-bit, unsigned is 1 extra
			# 9/10 for 64-bit
			# r12k paper, p13

[AddressIssueX]
blockName   = "IntWin"
winSize      = 16         #?? 
recycleAt    = 'Execute'  # Recycle entries at : Execute|Retire

schedNumPorts = 2  # ??
schedPortOccp = 1  # ??
wakeUpNumPorts= 0  # ??
wakeUpPortOccp= 0  # ??
wakeupDelay   = 0  # ??
schedDelay    = 0  # ?? 


iStoreUnit   = 'LDSTIssueX' # Renau - shared LD/ST cache port
iStoreLat    = 1   # ??

iLoadUnit    = 'LDSTIssueX'
iLoadLat     = 1   # r12k paper, p13 if in l1 cache.
		   # is this cumulative with cache hit rate?





#
# FP ALU
#
# For r12k, there are 5 floating point units
#  they are 3-stage pipelined, with a 1-cycle repeat rate
# adder
# multiplier
# divide
# square root
# load/store
# latency and repeat rate are not necessarily the same

[FPClusterIssueX]
blockName   = "FPWin"
winSize     = 16        # ??
recycleAt   = 'Execute' # Recycle entries at : Execute|Retire
schedNumPorts = 2 # Renau
schedPortOccp = 1 # ??
wakeUpNumPorts= 0 # Renau
wakeUpPortOccp= 0 # Renau
wakeupDelay   = 0 # Renau
schedDelay    = 0 # ??

fpALUUnit    = 'FP0IssueX'
fpALULat     = 2  # r12k paper p16

fpMultUnit   = 'FP1IssueX'  # Renau
fpMultLat    = 2  # 4 if it's a multiply/add
		  # r12k p16
		  
fpDivUnit    = 'FP1IssueX' # Renau
fpDivLat     = 12 # 12 for 32bit, 19 for 64-bit
		  # r12k p16

[LDSTIssueX]
Num = 1 # ??
Occ = 1 # ??

[ALUIssueX]
Num = 1 # Renau
Occ = 1 # ??

[MDIssueX] # Renau - muldiv for int
Num = 1
Occ = 8 # Renau - Shared by mult and div.  32b mult 6, 64b mult 10,
        # 32 bit div 35, 64b div 67.
	# What is the real mix?  Not easy to model with sesc

[FP0IssueX]
Num = 1 # ??
Occ = 1 # ??

[FP1IssueX] # Renau - FP Mult/Div unit
Num = 1 
Occ = 2  # Renau - 2 cycle occupancy

###########################################
# BRANCH PREDICTOR
###########################################
# bits 12:2 used to index into 2048 entry saturating 
# 2-bit counter
#
# 4 "shadow" copies of reg file.  When misprediction, 
# takes 2 cycles to recover on r12k (1 cycle on r10k)
#
# r12k has optional 8-bit global history that can be hashed
#   into main branch index. Linux leaves this alone, disabled
#   by default (r12k p19)

# always taken branch predictor, which can be enabled
# in hardware on r12k

[BPredIssueX]
type = "Taken"
btbSize        = 1
btbBsize       = 1
btbAssoc       = 1
btbReplPolicy  = 'LRU'
rasSize        = 1

#[BPredIssueX]
#type           = "2bit" 
#size	       = 2048	   # r12k paper, p5
#rasSize	       = 4	   # r12k manual page 236
#btbSize	       = 32        # r12k paper p5
#btbAssoc       = 2	   # r12k paper p5
#btbBsize       = 1         # ??
#btbReplPolicy  = 'LRU'     # ??
#bits           = 2	   # (saturating bits.  why is this not 
                           #  documented better)
BTACDelay      = 2	   # Renau			   

###############################
# physically tagged
# 32kB 2-way 64-byte lines
# from dmesg on actual machine
# also has a parity bit
# stored in a 36-bit pre-decoded format
# LRU
# Can fetch 4 consecutive instructions, but can't cross a block boundary

[InstL1]
deviceType  = 'icache'
blockName   = "Icache"
size        = 32*1024
assoc       = 2
bsize       = 64
writePolicy = 'WB'  # n/a
replPolicy  = 'LRU' #
numPorts    = 1     # Renau
portOccp    = 1     #??
hitDelay    = 2     # cycles? if so, r12k p6
missDelay   = 0     #??
MSHR        = 'InstL1MSHR' #??
lowerLevel  =  "L2Cache L2 shared"

[InstL1MSHR]
size = 4        # Renau
		# ?? is this bytes? entries?
type = 'full'    # ??
bsize = 64       # ??

################################
# Memory Subsystem (L1)
################################
#  32kB, 2-way, linesize 32 bytes
# each byte has parity bit
# two identical banks selected by address bit 5
# physically tagged

[DataL1]
deviceType   = 'cache'
blockName    = "Dcache"
MSHR         = "DL1MSHR"
size         = 32*1024
assoc        = 2
skew         = false  #??
bsize        = 32
replPolicy   = 'LRU' #
numPorts     =  2 #Renau
portOccp     =  1 #??
hitDelay     =  2 # cycles? if so r12k p6
		  # lmbench shows 6.6ns, so that matches 2 cycles

missDelay    =  1 #??
writePolicy  = "WB" # r12k p7
lowerLevel   = "CommonBus Bus shared" #??

[DL1MSHR]
type = 'full' #??
size = 8      # Renau - 4MSHR entries in R10K
              #         but can handle up to 4 pending per entry
	      #         SESC can't do this, approx with 8?
bsize = 64    #??


##############################
# 2MB, 2-way, 128 bytes
# from dmesg
# each quadword has 9-bit ECC and a parity bit
# correction pipeline takes 2 cycles
# latency ~10 cycles

# has a 16kB way-predict table

# the tags re on-chip, cache itself off-chip

[L2Cache]
deviceType   = 'cache'
blockName    = "L2"
size         = 2*1024*1024
assoc        = 2
bsize        = 128
writePolicy  ='WB'  # r12k p7
replPolicy   ='LRU' #??
numPorts     =  1   #??
portOccp     =  1   #??
hitDelay     = 10   # r12k p 6
		    # lmbench measurements show 47.3ns or about 14cycles 
		    
		    
missDelay    =  4   #??
MSHR         = 'MSHRL2' #??
lowerLevel  = "MemoryBus"

[MSHRL2]
type = 'full' # ??
size = 32     # ??
bsize = 64    # ??

[CommonBus]
deviceType  = 'bus'
busWidth    =      32
busLength   =     7500  # 7.5 mm ??
numPorts    =        1  # Renau
portOccp    =        1
delay       =        1  # Renau
buffWCReqs  =        1
lowerLevel  =  "L2Cache L2 shared"


[MemoryBus]
deviceType    = 'bus'
numPorts      = 1
portOccp      = 168    # Renau - Since the processor operates at 300MHz and 
                       # the L2 cache has 128bytes, to have around 300MB/s 
		       # when you just need 1 request every 128 cyles. To
                       # make it closer to 220MB/s use 168 cycles port 
		       # occupancy (128/168*300 = 220MB/s)


                       # lmbench shows ~220MB/s bandwidth
		       #   220MB/s / 128B = 1.802e6 cachelines/s
		       #                   = .005946 cachelines/cycle
		       # so, 168 cycles/cacheline?
			
delay         = 15
lowerLevel    = "Memory Memory"

# The Octane we have has a peak bandwidth 1.0GB/s system bus
# 2GB of SDRAM memory, possibly PC100 (100MHz)

[Memory]
deviceType    = 'niceCache'
size          = 128
assoc         = 1
bsize         = 64
writePolicy   = 'WB'
replPolicy    = 'LRU'
numPorts      = 1
portOccp      = 1
hitDelay      = 113   # According to lmbench our machine has 404.6ns delay
                      # clock cycle is 300MHz so 3.3ns
		      # so approximately 120 clock cycles
		      # renau - You have to discount the miss time 
		      # (21 cycles total), so 113 clk should be
		      # fine (404/3-21 ~ 113).
			 

missDelay     = 500
MSHR          = NoMSHR
lowerLevel    = 'voidDevice'

[NoMSHR]
type = 'none'
size = 128
bsize = 64

[voidDevice]
deviceType    = 'void'
