diff -r a2a79fe9655d src/cpu/base.hh
--- a/src/cpu/base.hh	Wed Nov 11 17:49:09 2009 -0500
+++ b/src/cpu/base.hh	Sat Nov 14 16:41:51 2009 -0500
@@ -275,6 +275,7 @@
     virtual BranchPred *getBranchPred() { return NULL; };
 
     virtual Counter totalInstructions() const { return 0; }
+    virtual Counter totalUops() const { return 0; }
 
     // Function tracing
   private:
@@ -298,6 +299,18 @@
 
   public:
     static int numSimulatedCPUs() { return cpuList.size(); }
+   
+    static Counter numSimulatedUops()
+    {
+        Counter total = 0;
+
+        int size = cpuList.size();
+        for (int i = 0; i < size; ++i)
+            total += cpuList[i]->totalUops();
+
+        return total;
+    }
+   
     static Counter numSimulatedInstructions()
     {
         Counter total = 0;
diff -r a2a79fe9655d src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc	Wed Nov 11 17:49:09 2009 -0500
+++ b/src/cpu/simple/atomic.cc	Sat Nov 14 16:41:51 2009 -0500
@@ -675,8 +675,10 @@
                 fault = curStaticInst->execute(this, traceData);
 
                 // keep an instruction count
-                if (fault == NoFault)
-                    countInst();
+                if (fault == NoFault) {
+		   if (curStaticInst->isLastMicroop()) countRealInst();
+                   countInst();
+		}
                 else if (traceData) {
                     // If there was a fault, we should trace this instruction.
                     delete traceData;
diff -r a2a79fe9655d src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc	Wed Nov 11 17:49:09 2009 -0500
+++ b/src/cpu/simple/base.cc	Sat Nov 14 16:41:51 2009 -0500
@@ -86,6 +86,7 @@
 
     tc = thread->getTC();
 
+    numUops = 0;
     numInst = 0;
     startNumInst = 0;
     numLoad = 0;
diff -r a2a79fe9655d src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh	Wed Nov 11 17:49:09 2009 -0500
+++ b/src/cpu/simple/base.hh	Sat Nov 14 16:41:51 2009 -0500
@@ -179,11 +179,17 @@
     Counter numInst;
     Counter startNumInst;
     Stats::Scalar numInsts;
+    Counter numUops;
 
+    void countRealInst() 
+    {
+        numInsts++;
+    }
+   
     void countInst()
     {
         numInst++;
-        numInsts++;
+        numUops++;
 
         thread->funcExeInst++;
     }
@@ -192,7 +198,12 @@
     {
         return numInst - startNumInst;
     }
-
+   
+    virtual Counter totalUops() const
+    {
+        return numUops;
+    }   
+   
     // Mask to align PCs to MachInst sized boundaries
     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 
diff -r a2a79fe9655d src/cpu/thread_state.hh
--- a/src/cpu/thread_state.hh	Wed Nov 11 17:49:09 2009 -0500
+++ b/src/cpu/thread_state.hh	Sat Nov 14 16:41:51 2009 -0500
@@ -153,6 +153,7 @@
     Counter numInst;
     /** Stat for number instructions committed. */
     Stats::Scalar numInsts;
+    Stats::Scalar numUops;
     /** Stat for number of memory references. */
     Stats::Scalar numMemRefs;
 
diff -r a2a79fe9655d src/sim/stat_control.cc
--- a/src/sim/stat_control.cc	Wed Nov 11 17:49:09 2009 -0500
+++ b/src/sim/stat_control.cc	Sat Nov 14 16:41:51 2009 -0500
@@ -85,8 +85,10 @@
 
     Stats::Value simTicks;
     Stats::Value simInsts;
+    Stats::Value simUops;   
     Stats::Value simFreq;
 
+   
     Global();
 };
 
@@ -99,6 +101,12 @@
         .precision(0)
         .prereq(simInsts)
         ;
+   
+    simUops
+        .functor(BaseCPU::numSimulatedUops)
+        .name("sim_uops")
+        .desc("Number of uops simulated")
+        ;   
 
     simSeconds
         .name("sim_seconds")