time build/ARM/gem5.opt configs/example/se.py -c ../susan -o "../input_large.pgm ../output_large_smoothing.pgm -s" ---------- Begin Simulation Statistics ---------- sim_seconds 0.215333 # Number of seconds simulated sim_ticks 215333193000 # Number of ticks simulated final_tick 215333193000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 549996 # Simulator instruction rate (inst/s) host_op_rate 649041 # Simulator op (including micro ops) rate (op/s) host_tick_rate 427515763 # Simulator tick rate (ticks/s) host_mem_usage 621472 # Number of bytes of host memory used host_seconds 503.69 # Real time elapsed on the host sim_insts 277024807 # Number of instructions simulated sim_ops 326912205 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1523115956 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 93271562 # Number of bytes read from this memory system.physmem.bytes_read::total 1616387518 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1523115956 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1523115956 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 2987780 # Number of bytes written to this memory system.physmem.bytes_written::total 2987780 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 380778989 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 79384948 # Number of read requests responded to by this memory system.physmem.num_reads::total 460163937 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 834544 # Number of write requests responded to by this memory system.physmem.num_writes::total 834544 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 7073298523 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 433149951 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 7506448474 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7073298523 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7073298523 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 13875148 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 13875148 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7073298523 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447025099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7520323622 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 24 # Number of system calls system.cpu.numCycles 430666387 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 277024807 # Number of instructions committed system.cpu.committedOps 326912205 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 297628117 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 58563 # Number of float alu accesses system.cpu.num_func_calls 226682 # number of times a function call or return occured system.cpu.num_conditional_control_insts 27338218 # number of instructions that are conditional controls system.cpu.num_int_insts 297628117 # number of integer instructions system.cpu.num_fp_insts 58563 # number of float instructions system.cpu.num_int_register_reads 1517466421 # number of times the integer registers were read system.cpu.num_int_register_writes 427849142 # number of times the integer registers were written system.cpu.num_fp_register_reads 121929 # number of times the floating registers were read system.cpu.num_fp_register_writes 79139 # number of times the floating registers were written system.cpu.num_mem_refs 80220797 # number of memory refs system.cpu.num_load_insts 79385571 # Number of load instructions system.cpu.num_store_insts 835226 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 430666387 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles ---------- End Simulation Statistics ---------- info: Increasing stack size by one page. hack: be nice to actually delete the event here Exiting @ tick 215333193000 because target called exit() real 8m24.489s user 8m23.819s sys 0m0.052s