Can Hardware Performance Counters be Trusted?

by Vincent M. Weaver and Sally A. McKee

This page contains information on the paper "Can Hardware Performance Counters be Trusted?" which was presented at the 2008 IEEE International Symposium on Workload Characterization (IISWC) on 16 September 2008 in Seattle, Washington.

This paper investigates how deterministic the retired instruction performance counter is across multiple generations of x86 processors. Various workarounds are presented that reduce variation on x86 Linux systems.

The most complete version of this paper is the tech report version, CSL-TR-2008-1051.

• Can Hardware Performance Counters be Trusted? (tr1051_08.pdf) by V. M. Weaver and S. A. McKee

Here is the version as it appeared in the conference proceedings:

• Can Hardware Performance Counters be Trusted? (iiswc08_inst.pdf) by V. M. Weaver and S. A. McKee [IEEE copyright rules apply]

Here are the slides from the presentation:

• IISWC08 Slides

The perfmon2 tool and patches used for gathering performance counter data can be found at the link below. All changes we have made to improve perfmon support have been submitted to the perfmon maintainers and are included in the newest releases.

• Perfmon2 Homepage

Qemu:

• We used qemu-0.9.1 patched with this patch: qemucount.patch

Valgrind:

• We used the tool here, patched against Valgrind 3.3.0, using the --instr_count_only options: exp-bbv

Pin:

• We used the icount1.cpp tool that came with Pin pin-2.4-19012-gcc.4.0.0-ia32-linux to count retired instructions.

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