L1 Data Cache Misses
PAPI_L1_DCM
Care must be taken when looking at cache-related performance counters, as
cache behavior can be affected by the kernel and other processes.
x86 and x86_64
- Pentium Pro, II, III
- Atom
- Core Duo (not Core2)
- Core2
- Nehalem
- There is unfortunately no good way to get L1 Dcache misses on
Nehalem. The obvious way would be
L1D_CACHE_LD:I_STATE + L1D_CACHE_ST:I_STATE but these counters
have issues, as described in errata AAK119 as well as
statements
from Intel
- AMD
- DATA_CACHE_MISSES - note that on Opteron and newer
the hardware prefetcher prefethces into L1, which can drastically
alter the miss rates from what is expected.
- Netburst (Pentium 4, Pentium D)
- There are rumors that such a counter exists, but lots of
problems trying to figure it out.
one attempt
a response
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