Store Instructions

x86 and x86_64

• Pentium Pro, II, III
• AMD
  • no counter available
• Atom
  • no counter available
• Core2
  • INST_RETIRED:STORES - r5002c0:u
    This counter is notable as it is one of the few deterministic performance counters available.
    
• Nehalem, Nehalem EX
  • MEM_INST_RETIRED:STORES - r50020b:u
    The cpuid instruction counts as a store.
    The sfence instruction counts as a store.
    The clflush instruction counts as a store.
    The mfence instruction counts as a store.
    
• SandyBridge
  • MEM_UOP_RETIRED:ANY_STORES - r5382d0:u
    As with Pentium 4, counts uops not ops.
• Pentium D
  • FRONT_END_EVENT:NBOGUS,UOPS_TYPE:TAGSTORES
    The cpuid instruction counts as a store.
    The enter instruction counts an extra store for each nested stack frame.
    The fbstp instruction counts as two stores.
    The fstps instruction counts as two stores.
    The fstpt instruction counts as two stores.
    The fstenv instruction counts as seven stores.
    The fsave instruction counts as 23 stores.
    The fxsave instruction counts as 25 stores.
    The movups (store) instruction counts as two stores.
    The sfence instruction counts as a store.
    The movupd (store) instruction counts as two stores.
    The movdqu (store) instruction counts as two stores.
    The clflush instruction counts as a store.
    The maskmovdqu instruction counts as two stores.
    The mfence instruction counts as a store.
    The rep stos instructions count stores in 16B blocks (unless going backwards where it's indivudual).
    The rep movs instruction counts stores in 16B blocks.