perf_event Generalized Events

This is an examination of which events are used by the perf_event Generalized Events (the ones shown when you run perf list). It is not possible to determine which events are being used from kernel space, you have to read the kernel source.

I personally agree with the PAPI philosophy that pre-defined events should be defined in userspace, not in the kernel like perf_events does. However that doesn't seem likely to change.

This started out mainly as a sanity check to make sure PAPI is using good events, but it turns out to be the opposite, the kernel is often using improper events.

AMD fam10h

perf_event name	perf_event libpfm4 equiv	perf_event raw	PAPI name	PAPI libpfm4 equiv	PAPI raw
cycles	CPU_CLK_UNHALTED	0x530076	PAPI_TOT_CYC	CPU_CLK_UNHALTED	0x530076
instructions	RETIRED_INSTRUCTIONS	0x5300c0	PAPI_TOT_INS	RETIRED_INSTRUCTIONS	0x5300c0
cache-references	INSTRUCTION_CACHE_FETCHES	0x530080
cache-misses	INSTRUCTION_CACHE_MISSES	0x530081
branches	RETIRED_BRANCH_INSTRUCTIONS	0x5300c2	PAPI_BR_INS	RETIRED_BRANCH_INSTRUCTIONS	0x5300c2
branch-misses	RETIRED_MISPREDICTED_BRANCH-_INSTRUCTIONS	0x5300c3	PAPI_BR_MSP	RETIRED_MISPREDICTED_BRANCH-_INSTRUCTIONS	0x5300c3
bus-cycles	N/A
stalled-cycles-backend	DECODER_EMPTY	0x5300d0	PAPI_STL_ICY	DECODER_EMPTY	0x5300d0
stalled-cycles-frontend	DISPATCH_STALLS	0x5300d1	PAPI_RES_STL	DISPATCH_STALLS	0x5300d1
l1-dcache-loads	DATA_CACHE_ACCESSES	0x530040	PAPI_L1_DCR	N/A
l1-dcache-load-miss	DATA_CACHE_MISSES:1 (?)	0x530141	PAPI_L1_LDM	N/A
l1-dcache-stores	DATA_CACHE_REFILLS:SYSTEM	0x5300142	PAPI_L1_DCW	N/A
l1-dcache-store-misses	N/A	0	PAPI_L1_STM	N/A

Known bad events used by the kernel in the past on AMD:

branches was RETIRED_TAKEN_BRANCH_INSTRUCTIONS from 2.6.31 - 2.6.35
branch-misses was RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED from 2.6.31 - 2.6.35
PERF_COUNT_HW_CACHE_ITLB:READ:MISS had a bogus umask value of 0 2.6.31 - 2.6.37
PERF_COUNT_HW_CACHE_DTLB:READ:MISS had a bogus umask value of 0 2.6.31 - 2.6.37
cache-references was INSTRUCTION_CACHE_FETCHES 2.6.31 - current
cache-misses was INSTRUCTION_CACHE_MISSES 2.6.31 - current
L1-icache-prefetches was an improper event 2.6.31 - current
l1-dcache-stores was DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE:SYSTEM from 2.6.31 - current
l1-dcache-loads includes both loads and stores, 2.6.31 - current

Intel

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