Valgrind Ruby

The point of this project is to hook up Valgrind to a multi-core cache simulator.

Initial plan is to strip Ruby out of m5 (which for some reason is where Ruby work is happening these days, rather than at GEMS).

The following documents the steps I am doing, mainly as a reminder to myself.

Downloading and Building m5

To downlaod initial dev tree "hg clone http://repo.m5sim.org/m5"
To update "hg pull; hg update"
Make all of the targets, if you want to test:
- To build Alpha syscall emulation mode: "scons build/ALPHA_SE/m5.opt"
- To build MIPS LE syscall mode: "scons build/MIPS_SE/m5.opt"
- To build SPARC syscall mode: "scons build/SPARC_SE/m5.opt"
- To build ARM LE syscall mode: "scons build/ARM_SE/m5.opt"
- To build X86 syscall mode: "scons build/X86_SE/m5.opt"

Testing m5

Debugging

/fusion/research4/vince/m5/m5/build/X86_SE/m5.opt --trace-flags=Exec --outdir ../m5_output/x86 /fusion/research4/vince/m5/m5//configs/example/se.py -c ./ll.i386.fakeproc | less

Building ruby stand-alone

Benchmarks

ll

x86 spec2k

See a more detailed page here: m5 x86_se spec2k status

multi-arch spec2k

As of 16 September 2009 for gcc.expr from spec2k:

Alpha - cycles 5264907610000 wallclock 1:32:30.14 total
ARM - futex() unimplemented. Also "swp" instruction not implemented
Mipsel - I don't have the mipsel toolchain set up
SPARC - crashes 661532835500 cycles in
x86_64 - getrlimit unimplemented. also warnings about unimplemented floating point ops

Patches to m5

Fix for SPARC udivcc instructions - ~~sent 15 September 2009~~ applied
x86 32-bit syscall additions - ~~sent 14 September 2009~~ applied
Fix for x86 loop instructions - ~~sent 15 September 2009~~ fixed in a different form
sysinfo syscall support - ~~sent 14 September 2009~~ applied
sparc syscall additions - sent 29 July 2009
mips compile fixes applied

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