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CMSIS-Core (Cortex-M)
Version 5.3.0
CMSIS-Core support for Cortex-M processor-based devices
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![]() ![]() | Union type to access the Application Program Status Register (APSR) |
![]() ![]() | Setup information of a single MPU Region |
![]() ![]() | Union type to access the Control Registers (CONTROL) |
![]() ![]() | Structure type to access the Core Debug Register (CoreDebug) |
![]() ![]() | Structure type to access the Data Watchpoint and Trace Register (DWT) |
![]() ![]() | Structure type to access the Floating Point Unit (FPU) |
![]() ![]() | Union type to access the Interrupt Program Status Register (IPSR) |
![]() ![]() | Structure type to access the Instrumentation Trace Macrocell Register (ITM) |
![]() ![]() | Structure type to access the Memory Protection Unit (MPU) |
![]() ![]() | Structure type to access the Nested Vectored Interrupt Controller (NVIC) |
![]() ![]() | Structure type to access the System Control Block (SCB) |
![]() ![]() | Structure type to access the System Control and ID Register not in the SCB |
![]() ![]() | Structure type to access the System Timer (SysTick) |
![]() ![]() | Structure type to access the Trace Port Interface Register (TPI) |
![]() ![]() | Union type to access the Special-Purpose Program Status Registers (xPSR) |