| Due | Assignment |
| 1) Wed. Sept. 9: |
Chapter 2 problems (Verilog 2nd or 3rd ed, VHDL 3rd ed.): 2, 7b, 7c, 8, 12, 13, 17, 21, 22 (or if you have an earlier edition of either text): 2, 6b, 6c, 7, 11, 12, 16, 20, 21) |
| 2) Mon., Sept. 14: |
1. If the SOP form for f* = AB*C*+A*B,
then give the POS form for f (where * means complement the preceding character) 2. Use DeMorgan's Theorem to find f if f* = (A + BC)D + EF. (Do not expand, answer should have only one instance of each variable). 3a. Give a truth table for the function f = ABC* + BD. 3b. Write f as a Sum of Products 3c. Write f in canonical minterm form 3d. Write f as a Product of Sums. 3e. Write f in canonical maxterm form 4a, 4b. Text problems 2.51 and 2.52 (3rd edition Verilog text) or 2.37 and 2.38 (in other newer editions). (Problem is only in newer editions. Questions say to implement the function in Figure 2.26 using 1) only NANDs, 2) only NORs.- Use figure 2.20 for 1st ed. VHDL text; use figure 2.24 for 1st ed. Verilog text |
| 3) Fri., Sept. 18: | Verilog Edition 3: Chapter 2 problems 37, 38, 39, 40, 42, 46. For all other editions: Chapter 4 problems 1, 2, 3, 4, 6, 10. |
| 4) Wed., Sept. 23: | Assignment is here. |
| 5) Mon., Sept. 28: |
Use Quine-McCluskey (i.e., tabular) method to find a minimal
SOP for the following: 1) f(X,Y,Z) = Sum m(2,3,4,5); 2) f(A,B,C,D) = Sum m(0,1,4,5,12,13); 3) f(A,B,C,D) = Sum m(1,5,7,8,9,13,15) + d(4,14). 4) Hazard problem: Design a hazard free SOP for f(A,B,C,D) = Σ m(0,1,4,5,6,7,9,11,14,15) |
| 6) Wed., Oct. 7: |
Verilog Edition 3: Chapter 8 problems
7 and 8.
For all other editions: Chapter 4 problems
20 and 21. |
| 7) Wed., Oct 14: | Verilog Edition 3: Chapter 3 problems 1, 2, 3, 4, 7. For all other editions: Chapter 5 problems 1, 2, 3, 4, 7. |
| 8) Mon., Oct 19: | Verilog Edition 3: Appendix B problems 1, 2, 3, 8, 10, 13. For all other editions: Chapter 3 problems 1, 2, 3, 8, 10, 13. For problem 2 see section B.8.8 (or 3.9). For problem 10, see hint for problem 13. |
| 9) Fri., Oct 23: | Verilog Edition 3: Five Appendix B problems: 36, 38 (error in book, use Fig. B.69), 40, 42, 45. For all other editions: Chapter 3 problems 36, 38, 40, 42, 45. |
| 10) Wed., Oct. 28: | Verilog Edition 3: Appendix B problem 25 For all other editions: Chapter 3 problem 25 Also determine Fan Out and Noise Margin for a 74L00 device driving 74L00 devices. Repeat for a 74L00 device driving 74LS00 devices. TTL spec sheet is here. |
| 11) Mon., Nov. 2: |
1) 4.1 in Verilog 3rd edition (6.1 in all other editions of the text) Do three ways: a)
directly with no inversions anywhere b) least logic
(smallest gate) c) decoder has inverted outputs; 2) 4.4 in Verilog 3rd edition (6.4 in all other editions of the text) Use a 2:1 mux and no other logic (inverter is OK); 3) Modified Fig. 4.21 (see note below) in Verilog 3rd edition (Fig. 6.25 in all other editions): a) implement segment "a" using an 8:1 mux and no other logic, b) implement segment "a" using a 4:1 mux and one other gate, c) implement segment "f" with 4:1 mux and no other logic. Note: The Verilog 3rd edition figure shows a hex-to-7-segment display and I want you to use a BCD-to-7-segment display as is given in the other editions of the text. Therefore, for that edition replace the last 6 rows of the table with don't cares. |
| 12) Wed., Nov. 18: | Verilog Edition 3: Chapter 5 problems 1, 2, 5, 7. For all other editions: Chapter 7 problems 1, 3, 6, 8. |
| 13) Mon., Nov. 23: | Verilog Edition 3: Chapter 5 problems 15, 16, 17, 18 For all other editions: Chapter 7 problems 16, 17, 18, 19. |
| 13.5) Fri., Dec. 4: | Watch the two "Homework Videos" posted in Brightspace under Week 14. |
| 14) Mon., Dec. 7: | Give a state graph and a state table for your design for Lab 9. |