# ECE 275 --- Sequential Logic SystemsAssignments

## Homework Assignments (due at the start of class):

 Due Assignment 1) Wed. Sept. 9: Chapter 2 problems (Verilog 2nd or 3rd ed, VHDL 3rd ed.): 2, 7b, 7c, 8, 12, 13, 17, 21, 22 (or if you have an earlier edition of either text): 2, 6b, 6c, 7, 11, 12, 16, 20, 21) 2) Mon., Sept. 14: 1. If the SOP form for f* = AB*C*+A*B, then give the POS form for f (where * means complement the preceding character)  2. Use DeMorgan's Theorem to find f  if  f* = (A + BC)D + EF. (Do not expand, answer should have only one instance of each variable).  3a. Give a truth table for the function f = ABC* + BD.  3b. Write f  as a Sum of Products  3c. Write f  in canonical minterm form  3d. Write f  as a Product of Sums.  3e. Write f  in canonical maxterm form4a, 4b. Text problems 2.51 and 2.52 (3rd edition Verilog text) or 2.37 and 2.38 (in other newer editions). (Problem is only in newer editions. Questions say to implement the function in Figure 2.26 using 1) only NANDs, 2) only NORs.- Use figure 2.20 for 1st ed. VHDL text; use figure 2.24 for 1st ed. Verilog text 3) Fri., Sept. 18: Verilog Edition 3: Chapter 2 problems 37, 38, 39, 40, 42, 46. For all other editions: Chapter 4 problems 1, 2, 3, 4, 6, 10. 4) Wed., Sept. 23: Assignment is here. 5) Mon., Sept. 28: Use Quine-McCluskey (i.e., tabular) method to find a minimal SOP for the following:   1) f(X,Y,Z) = Sum m(2,3,4,5);   2) f(A,B,C,D) = Sum m(0,1,4,5,12,13);   3) f(A,B,C,D) = Sum m(1,5,7,8,9,13,15) + d(4,14).   4) Hazard problem: Design a hazard free SOP for f(A,B,C,D) = Σ m(0,1,4,5,6,7,9,11,14,15) 6) Wed., Oct. 7: Verilog Edition 3: Chapter 8 problems 7 and 8. For all other editions: Chapter 4 problems 20 and 21. 7) Wed., Oct 14: Verilog Edition 3: Chapter 3 problems 1, 2, 3, 4, 7. For all other editions: Chapter 5 problems 1, 2, 3, 4, 7. 8) Mon., Oct 19: Verilog Edition 3: Appendix B problems 1, 2, 3, 8, 10, 13. For all other editions: Chapter 3 problems 1, 2, 3, 8, 10, 13. For problem 2 see section B.8.8 (or 3.9). For problem 10, see hint for problem 13. 9) Fri., Oct 23: Verilog Edition 3: Five Appendix B problems: 36, 38 (error in book, use Fig. B.69), 40, 42, 45. For all other editions: Chapter 3 problems 36, 38, 40, 42, 45. 10) Wed., Oct. 28: Verilog Edition 3: Appendix B problem 25 For all other editions: Chapter 3 problem 25 Also determine Fan Out and Noise Margin for a 74L00 device driving 74L00 devices. Repeat for a 74L00 device driving 74LS00 devices. TTL spec sheet is here. 11) Mon., Nov. 2: 1) 4.1 in Verilog 3rd edition (6.1 in all other editions of the text) Do three ways: a) directly with no inversions anywhere b) least logic (smallest gate) c) decoder has inverted outputs;  2) 4.4 in Verilog 3rd edition (6.4 in all other editions of the text) Use a 2:1 mux and no other logic (inverter is OK);  3) Modified Fig. 4.21 (see note below) in Verilog 3rd edition (Fig. 6.25 in all other editions): a) implement segment "a" using an 8:1 mux and no other logic, b) implement segment "a" using a 4:1 mux and one other gate, c) implement segment "f" with 4:1 mux and no other logic. Note: The Verilog 3rd edition figure shows a hex-to-7-segment display and I want you to use a BCD-to-7-segment display as is given in the other editions of the text. Therefore, for that edition replace the last 6 rows of the table with don't cares. 12) Wed., Nov. 18: Verilog Edition 3: Chapter 5 problems 1, 2, 5, 7. For all other editions: Chapter 7 problems 1, 3, 6, 8. 13) Mon., Nov. 23: Verilog Edition 3: Chapter 5 problems 15, 16, 17, 18 For all other editions: Chapter 7 problems 16, 17, 18, 19. 13.5) Fri., Dec. 4: Watch the two "Homework Videos" posted in Brightspace under Week 14. 14) Mon., Dec. 7: Give a state graph and a state table for your design for Lab 9.

By Friday, Sept. 4: Read through the end of Section 2.5.
By Wednesday, Sept. 9: Read through the end of Section 2.8.
By Friday, Sept. 11: Read through the end of Section 2.10
By Monday, Sept 14: Verilog, 3rd Ed: Read 2:11 to 2.14 and 2.17, Other editions: Read 4.1 to 4.4 and 2.12.
By Wednesday, Sept 16: Verilog, 3rd Ed: Read 2:11 to 2.14 and 2.17, Other editions: Read 4.1 to 4.4 and 2.12.
By Friday, Sept 18: Verilog, 3rd Ed: Read 2.15, Other editions: Read 4.5
By Monday, Sept. 21: Verilog, 3rd Ed: Read 8.3.1 and 8.4.1, Other editions: Read 4.8 and 4.9
(Note that 1st edition VHDL text does not include a discussion of the Tabular Method.)
By Monday, Sept. 28: Verilog, 3rd Ed: Read 8.1 and 8.2, Other editions: Read 4.6 and 4.7 (except 1st ed. VHDL Text Read sections 4.7 and 4.8).
By Wednesday, Sept. 30: Verilog, 3rd Ed: Read 3.1 through 3.3.3. Other editions: Read 5.1 through 5.3.3.
By Friday, Oct. 9: Verilog, 3rd Ed: Read Appendix B through B.4. Other editions: Read 3.1 through 3.4.
By Friday, Oct. 16: Verilog, 3rd Ed: Read B.5 through B.6. Other editions: Read 3.5 through 3.6.
By Monday, Oct. 19: Verilog, 3rd Ed: Read B.7 through B.8. Other editions: Read 3.7 through 3.9.
By Wednesday, Oct. 21: Verilog, 3rd Ed: Finish Appendix B. Other editions: Finish Chapter 3.
By Wednesday, Oct. 28: Verilog, 3rd Ed: Read 4.1 through 4.5. Other editions: Read 6.1 through 6.5.
By Friday, Oct. 30: Verilog, 3rd Ed: Section 4.8 Other editions: Read Section 6.8 (Examples of Solved Problems)
By Monday, Nov. 2: Verilog, 3rd Ed: Read 5.1 through 5.7. Other editions: Read 7.1 through 7.7.
By Wednesday, Nov. 4: Verilog, 3rd Ed: Read 5.8 through 5.11. Other editions: Read 7.8 through 7.11.
By Monday, Nov. 16: Verilog, 3rd Ed: Read 6.1 through 6.3. Other editions: Read 8.1 through 8.3.
By Monday, Nov. 23: Verilog, 3rd Ed: Read 6.5, 6.6 and 6.7. Other editions: Read 8.5, 8.6 and 8.7.

## Lab Assignments:

Lab 1 information -- beginning Sept. 14.     Video you will use for setup
Lab 2 information -- beginning Sept. 21.     Lab 2 files:   lab2part2top.v, lab2part3top.v, DE0_TOP.qsf, part1solution.png, lab02note.txt
Lab 3 information -- beginning Sept. 28.
Also, here is a link to the manual for the DE0. You may not need it directly, but it will help increase your understanding of our boards
Lab 4 information -- beginning Oct. 5.
Lab 5 information -- beginning Oct. 12.
Lab 6 information -- beginning Oct. 19. Two-week lab.
Lab 7 information -- beginning Nov. 2. Two-week lab.
Lab 8 information -- beginning Nov. 16.
Lab 9 information -- beginning Nov. 30.
For debouncing the clock input, include the files DEBOUNCE.VHD and CLK_DIV.VHD in your project.
This C program can check your state table lab9check.c
For prelab, have the design completed on paper before coming to lab. This will be checked at the beginning of lab and will count as one lab.

## Class Notes:

Class notes from August 31
Class notes from September 2
Class notes from September 4
Class notes from September 9
Class notes from September 14
Class notes from September 16
Class notes from September 18
Class notes from September 21
Class notes from September 25 - Hazards
Class notes from September 28
Class notes from September 30
Class notes from October 2
Class notes from October 7 & 9
Class notes from October 14 & 16 ( & 19)
Class notes from October 19 & 21
Class notes from October 23 & 26
Class notes from October 26
Class notes from October 28 & 30 & Nov.2
Class notes from November 2 & 4
Class notes from November 6
Class notes from November 13
Class notes from November 16
Class notes from November 18
Annotated parity checker from November 18
Annotated Up/Down counter from November 20 & 23
Class notes from November 23 & 30
Annotated sequence detector from December 2
Annotated sequence detector implementation from December 2
Annotated state minimization using row reduction from Homework Video 1
Annotated state minimization using implication tables from Homework Video 2
State assignment example from December 4
Annotated state assignment writeup from December 4
Class notes regarding Lab 9 from December 7 & 9
Class notes on Moore sequence detector from December 7
Class notes on incompletely-specified problems from December 9
Class notes on Mealy-Moore conversions from December 9
Class notes from December 11

## Notes:

Some Knights and Knaves problems for fun   and with answers
K-Map examples from class
Pairty checker (Moore & Mealy - done in class
Up/Down Counter done in class
Example sequence detector done in class. Both Mealy and Moore example
Implementation of the sequence detector using D-ff, T-ff, and JK-ff
Minimizing the number of states using row reduction
Minimizing the number of states using an implication table
A writeup on the State Assignments using the example given in class
Converting a Mealy to Moore and vice-versa.

FYI draw.io has a nice online way to draw state diagrams, flowcharts, etc. Let me know if you know of other (perhaps better) ways.